Various kinds of Analog-to-Digital Converters (ADC's) have been used in a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. Digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 102 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 102 may first be 0.5, then 0.25, then 0.375, then 0.313, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312 when comparing to a VIN of 0.312 volts. SAR 102 outputs the current register value to digital-to-analog converter (DAC) 100, which receives a reference voltage VREF and converts the register value to an analog voltage VDAC.
The input analog voltage VIN is applied to sample-and-hold circuit 104, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 104 is applied to the inverting input of comparator 106. The converted analog voltage VDAC is applied to the non-inverting input of comparator 106.
Comparator 106 compares the converted analog voltage VDAC to the sampled input voltage and generates a high output VCOMP when the converted analog voltage VDAC is above the sampled VIN, and the register value in SAR 102 is too high. The register value in SAR 102 can then be reduced.
When the converted analog voltage VDAC is below the sampled input voltage, comparator 106 generates a low output VCOMP to SAR 102. The register value in SAR 102 is too low. The register value in SAR 102 can then be increased for the next cycle.
The register value from SAR 102 is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 102 can first set the MSB D(N−1), then compare the converted analog voltage VDAC to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 102 to control sequencing.
FIG. 2 is a graph showing a SAR ADC resolving an input voltage. The register value in SAR 102 is initially set to one-half, or 10000. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102, so in the next iteration SAR 102 is set to one-quarter, or 01000. Comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the third iteration SAR 102 is set to three-eighths, or 01100. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102 in the third iteration, so in the fourth iteration SAR 102 is set to five-sixteenths, or 01010. Now comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the fifth iteration SAR 102 is set to 9/32, or 01011. The final comparison is that VIN is above the converted value, so the final result is 01011.
FIGS. 3A-C highlight metastability errors in an ADC. An Analog Front-End (AFE) of a receiver or similar circuit may include a SAR-ADC such as shown in FIG. 1 to digitize the received analog signal. One sample may be converted on every rising edge of a sampling clock, which may be synchronized to the SAR clock CLK (FIG. 1). Such a synchronous system can produce a digitized representation of the received signal, such digitized wave 114 shown in FIG. 3C. Two or more ADCs may be connected in parallel to interleave or pipeline conversions and support higher sampling rates.
Low-power systems such as small battery or inductive-powered Radio-Frequency Identification (RFID) tags operate at very high speeds. A synchronous ADC may be used with an over-sampling clock that is a multiple of the system clock. The fixed sample period may require many pulses of the over-sampling clock to perform the many steps in data conversion that are required for each data sample.
Another alternative is an asynchronous ADC that has a variable sampling time. An over-sampling clock may not be needed. However, the variable sampling time can cause noise on voltage references when interleaving is used, resulting in output errors. At some point in the design, an extra timing algorithm or synchronizer is needed to synchronize the asynchronous analog conversions back to the system clock. Metastability problems can occur, especially for small differential inputs.
In FIG. 3A, comparator 108 is a comparator within an ADC, such as comparator 106 in FIG. 1, or perhaps a buffer within a flip-flop or other storage element, such as in Approximation-Register SAR 102. Comparator 108 may have some feedback or exhibit properties of a bi-stable element even when a feedback loop is not explicitly included in its circuit schematic. Differential comparators may exhibit bistable characteristics especially when the two differential inputs are close to each other in value.
In FIG. 3B, a plot of the output voltages of comparator 108 is shown for various input voltages. When the two input voltages VIN+, VIN− are closer together, the outputs require more time to resolve to logic 1 and 0 states, as shown in curve 112, than when a larger input voltage difference VIN+, VIN− is applied, as shown in curve 110.
The comparator time-to-output TCOMP may be specified as the time until logic 1 and 0 are reached by its output under nominal VIN+, VIN− differences, as shown in curve 110. However, when the input voltages are closer together, as shown in curve 112, a time longer than TCOMP is required.
In a synchronous system, the output of comparator 108 must be sampled on a next clock edge. If that clock edge occurs at TCOMP, but the input voltages are as small as in curve 112, then the output is uncertain. A full logic 1 or logic 0 may not be latched in to the next stage. Metastability occurs in the comparator and can propagate downstream as the metastable signal is sampled and propagated through downstream logic and latches.
In asynchronous systems, such metastable signal may occur more often since the conversion time is not defined by a clocked signal. Thus both synchronous and asynchronous systems may suffer from metastability, especially when low power systems use low voltages.
In FIG. 3C, digitized wave 114 contains errors 116 that are caused by metastable events, such as when small voltages are compared. Such errors 116 may be dramatic and seriously alter the perceived digitized waveform. Such errors 116 are undesirable.
While some errors may be present in digitized wave 114, it is desired to reduce the size or magnitude of these errors 116. An ADC that detects metastability errors is desirable. An SAR-ADC that corrects metastability errors is particularly desirable to reduce the size of such errors.
What is desired is an error-detecting and error-correcting Successive-Approximation Register (SAR) analog-to-digital converter (ADC). A SAR-ADC that can reduce the magnitude of metastability errors is desirable.